Intel's Pat Gelsinger - chips with everything, but on an expanded menu

Profile picture for user mbanks By Martin Banks March 30, 2021
Intel's future is going to be built around the expected expansion of packaged systems using a 3D, layering and interconnect technology that can incorporate chips and devices from other vendors.


Pat Gelsinger at VMWorld

As predicted earlier this year, Pat Gelsinger is set to swing Intel whole-heartedly behind becoming the leading packaged systems producer rather than solely a chip producer, even though chip production is still going to be very much a prime-time activity. Indeed, it is set to get some heavy investment and be opened up to others as a chip foundry business.

This emerged as Gelsinger broke cover last week for the first time after being appointed as new CEO of Intel in January his year. His first press conference was held following a longish period of trouble for the company, subsequently compounded to some extent by wider troubles across much of the semiconductor chip industry.

Intel had badly fallen behind many of its competitors in its chip production process capabilities, especially in the all-important area of chip channel widths, where it had struggled to get down to 10 nanometers (nm) at a time when competitors were all down to 7nm and some down to 5nm. Then international politics reared its head as diplomatic relations between the USA and China deteriorated and the world was reminded that the vast majority of chips are now produced in China and Taiwan, with the former’s covetousness about the latter becoming a key bone of contention.

Gelsinger used his debut to do much more than calm troubled waters and declare the ship steady as she goes. As diginomica predicted, he not only pushed the idea that the ship is now moving along nicely, but that it is also heading in a different direction to most of its compatriots in the chip world.

The one missing point that he could have made was to refer back to his immediate last decade – as CEO of VMware. His experience of providing not ‘clever-techie’ code to business users (though it undoubtedly was), but business tools to business managers looking to solve business problems might just have been a statement that laid out the justification for such a change in direction, rather than promoting the company’s capabilities at the pointy-headed, nerdy-geek rocket-scientist end of the spectrum.

What’s in the package?

What he did announce showed why such a reference back could have been telling in getting across why a change in direction is important. That being said, the change in direction is still pretty obvious. The new Foveros 3D packaging is a core part of the company’s Integrated Device Manufacturer approach, which has been sufficiently upgraded for him to christen it IDM 2.0. The technique allows the company to stack various tiles vertically, including high performance logic such as CPU, graphics and AI processors, which he claims as a first. Foveros provides the opportunity to mix and match various IPs, while optimizing for performance and power efficiency. This is coupled with a second packaging development, the Embedded Multi-die Interconnect Bridge, which connects multiple, heterogeneous tiles within a single package.

The first example of the new approach in action is Ponte Vecchio, the first GPU based on the Xe-HPC microarchitecture. It will be initially used in Argonne National Laboratory's Aurora supercomputer, one of the first to provide 1 ExaFLOPS FP64 performance. This combines more than 40 different tiles from Intel, Samsung, and TSMC using a variety of process technologies, integrated into a single package demonstrating how the packaging technologies can deliver tailored products to meet customers markets and needs. In total the package contains more than 100 billion transistors manufactured in multiple process technologies.

As an idea of scale, Gelsinger made an interesting comparison:

Thirteen years ago, IBM introduced the world's first petaFLOPS supercomputer, which filled an entire, very large room. Now, right here in my hand, I have a petaFLOPS scale AI computer easily accessible to developers through Intel's one API toolkit.

The packaging technology will also be used on the company’s first step into 7nm scale processors, code named Meteor Lake. By 2023 this will be the frontline client CPU offering, featuring a new x86 architecture and modular design that utilises multiple manufacturing processes. This is intended to address the expected large industry transition as customers’ needs and workloads diversify and grow in complexity. Here, he sees all aspects of IT moving from `system on a chip’ to `system on package’.

Gelsinger has already acknowledged the fact that Intel under-estimated the importance of developments in UV Lithography - an important technology in chip manufacture - which is why its fell behind its competitors. But it is now a part, along with AMD and Motorola, of the Extreme Ultra-Violet Lithography Consortium, which is charged with commercialising technology developed by the US Department of Energy. He now expresses himself content that the chip production side is now on track again, though catching up, on that one front at least, may take a bit of endeavour, as some competitors are now already developing 3 nm technologies.

It is, however, possible to raise the question that, with the Foveros 3D packaging technologies, this may be less consequential than it sounds, for if the VMware-based business systems experience of Gelsinger filters through the Intel ranks, becoming a marketplace for those vendors with 3 nm technology chips may grow to be more important than investing in competing with them.

To be a foundry worker

Where he is keen to put his investment dollars, however, is in growing the company’s chip production capacity and capabilities. In particular, the goal is to fill the gap left by many of Intel’s compatriots, which have largely become product design houses driving production in off-shore foundries. Two factors are driving this change of direction - one is that the brute economics which drove the moves off-shore in the first place have mellowed considerably; the other is the increasing levels of political – and public - discontent between the USA and China. Having a significant majority of one of your most important `aw materials' for just about every other branch of modern life made overseas is not the best solution.

Intel itself is no stranger to using off-shore foundry facilities, especially for its memory devices, and it also one of the few US vendors to maintain manufacturing in the USA and Europe. But Gelsinger’s return is to herald a major sea-change in policy. The company is investing heavily in opening up foundry services of its own, particularly in the USA at its existing Arizona facility, he says:

The majority of leading-edge foundry capacity is concentrated in Asia, while the industry needs more geographically balanced manufacturing capacity. We plan to build two new fabs in Arizona located in Intel's Occotillo Campus. This represents an investment of approximately $20 billion, which will create over 3000 permanent jobs and 15,000 long term jobs in Arizona. We are excited to be partnering with the state of Arizona and the Biden administration on incentives that spur this type of domestic investment. We conservatively size the foundry opportunity as a $100 billion addressable market by 2025, with most of the growth coming from leading edge computing, which is our expertise.

This first phase will be followed by further foundry investment in the US, and in Europe. The Irish Development Agency has already revealed that Intel’s Leixlip Campus in County Kildare will be one of the targeted sites. The whole exercise is also being set up as Intel Foundry Services, a fully vertical standalone foundry business. This will be led by semiconductor industry veteran Dr. Randy Thacker, who will report directly to Gelsinger.

One of the signs that Intel was in trouble with its process technologies was that it cancelled its well-respected `main event’, the Intel Developer Forum, some three years ago. He is still obviously proud to have spoken at the first one, 24 years ago. So an important sign of his confidence in the new direction is that he also announced that the spirit of IDF wil be back this year with the launch of a new event series called Intel ON, planned for San Francisco this October.

My take

What seems clear here is that Intel is following a path that the chip sector has followed before. General purpose processors have moved to find ways of becoming field programmable gate arrays and systems on a chip etc in order to fill an inevitable hole that technology always produces. A new technology comes along and users are amazed at what it makes possible – usually an ability to do what has been done before at a far better price point and a reduction in the technical skills required to achieve. This is followed by a realisation that it can help achieve new capabilities and services that had always been thought ‘very difficult’ or indeed impossible. Next comes the realisation that the limitations of the general purpose version of the technology mean that capability X or service Y cannot be done well enough. This is when sub-plots emerge.

In earlier years of chips the GP processors (especially the superceded ones) started to turn up in SoCs and FPGAs, usually aimed at being the logic of specific function controllers. Currently this process can be seen best with the growth of AI/ML applications. Not so long ago it was a miracle that GP processors could make any of it work. Then the repetitive processing capabilities of one of those specialist processors, the Graphics Processing Unit (GPU) – designed to squirt out the rendering of video imaging at the highest possible speed (basically repetition of the same process with slightly different input variables) – also applied well to the needs of processing AI/ML applications. Hence the current surge of AI/ML applications out in the real world.

But this surge has only created its own problem, for once AI/ML starts to work well in a general purpose kind of way, users obviously want it to do a vast array of different, specific, functions, with the obvious consequence that using GPUs instead of (or in collaboration with) GP processors just comes up against that same inability to fulfil the growing desires of the users. So in the same way that SoCs emerged, Intel is following the same fundamental trail, this time with systems in a package.

Here the trick is likely to be found in the interconnection technology employed, and evidence of its importance may therefore come in the way it is accepted (or not) as a de facto industry standard by other chip makers that want to take their share of the new market. If you think about it, the technologies that have really made computing jump are not the processors, memory chips or storage devices. They have been the S-100 bus, ethernet, Bluetooth, USB and the rest that allowed different devices and systems to be combined by users into the functionality they required. If Intel can pull that off then will be possible to have devices from any and all chip design house and have them interconnect to build sub-system packages that can perform…..well, who knows, the applications won’t have been thought of yet.